1. Field of the Invention
The present invention relates to line codes used for a transmission, interconnection and storing apparatus, in particular to methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same which are capable of implementing an easier clock recovery, using one redundancy bit for a decoding operation, providing multiple frame synchronization code words, fully providing in-band and out-band signals, adapting a basic principle of a coding operation even when source byte data is not consist of 8 bit, and being easily adaptable to a hardware in a state that there are not DC spectrum components.
2. Description of the Conventional Art
According to the article of xe2x80x9cPrinciples of digital line codingxe2x80x9d by K. W. Cattermole, Int. J. electronics, Vol. 55, No. 1, pp. 3-33, 1983, it is known that the line coding is used for reliably recovering data bits from a serial bit stream. In addition, in the article of xe2x80x9cA DC-balanced, partitioned-block, 8B10B transmission codexe2x80x9d by A. X. Widmer and P. A. Franaszek, IBM J. Res. Develop., Vol. 5, pp. 440-451, 1983, the features such as a frame synchronization pattern and an in-band signal (special characters such as comma, identifier, empty character, etc.) are disclosed.
The line coding used for a physical layer in a communication transmission field requires a clock recovery and optical connection. Therefore, enough transition should be generated for a serial bit stream for the clock recovery. In addition, the DC frequency components should be 0 (zero) for implementing an AC coupling for the optical connection (R. M. Brooks and A. Jessop, xe2x80x9cLine coding for optical fiber systemsxe2x80x9d, Int. J. Electronics. Vol. 55, No. 1, pp. 81-120, 1983).
For implementing the above-described functions, a Manchester code, a CMI (Code Mark Inversion) code, and a 5B6B code are widely used. However, the above-described codes use the redundancy bits which decrease coding efficiency, and when the above-described codes are used in systems that process the codes byte by byte, it is very complicating and inconvenient.
In the field of the communication transmission, the scrambled zero non-return (scrambled NRZ) code which maximizes the coding efficiency is widely used. However, the scrambled NRZ secures DC frequency components of 0 statistically, not perfectly. The scrambled NRZ does not provide a frame synchronization pattern and an in-band signal.
In addition, a 8B10B code which has high coding efficiency in order to overcome the above-described problems in the computer network transmission field and is capable of providing an in-band signal (or a special character) is disclosed in P. A. Franaszek and A. X. Widmer, xe2x80x9cByte oriented DC balanced 8B10B partitioned block transmission codexe2x80x9d, U.S. Pat. Ser. No. 4,486,739. However, even though the above-described 8B10B code overcomes the problems encountered in the pre-codes, there are still problems that when the out-band signal or the frame synchronization pattern is inserted. In the 8B10B code, the out-band signal or the frame synchronization patterns should be inserted into a user source data field because a byte generally consists of 8 bits. Also the 8B10B code is impossible to obtain a uniform and symmetrical characteristic of coding rule when coding the source data is not consist of 8 bit such as 9-bit or 16-bit signal. Namely, since 2-bit redundancy bits are added to the 8-bit signal of the source data byte, when the frame synchronization pattern or a signal bit is inserted, it is impossible to add a redundancy bit to the code word so that user frame format should be changed. In addition, when coding the data except for the 8-bit signal, the code algorithm should be fully changed.
According to the article of W. A. Krzymein, xe2x80x9cTransmission performance analysis of a new class of line codes for optical fiber systemsxe2x80x9d, IEEE Trans. Commun., Vol. 37, No. 4, pp. 402-404, April 1989, the Partially flipped mB (m+1)B code is disclosed. This code forms a code word of m+1 bit by inserting a 1 bit redundancy bit into a m-bit source data character. In addition, this code implements a code operation using a disparity of a source data character and a running digital sum (RDS) which are code parameters. However, this code has a good coding efficiency and is simply used, but a synchronization code and in-band and out-band are not provided. Therefore, it is impossible to obtain good coding performance of a RDS, disparity, digital sum variation (DSV) and a run length.
It is an object of the present invention to provide methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same which are capable of providing transition and DC spectrum components of 0, using a 1-bit redundancy bit when a predetermined n-bit (n represents odd number) is coded, providing multiple frame patterns, providing an in-band and out-band signals enough, and detecting a bit error by a code violation detection based on a simple hardware.
In order to achieve the above objects, there are provided methods for coding nibble inversion codes and block inversion codes according to a first embodiment of the present invention which include the steps of a first step for adding a one redundancy bit to a n-bit (n represents an odd number larger than 3) source data and generating a pre-code, a second step for setting the pre-code as a code word when a disparity of the pre-code generated in the first step is 0 and the source data is not an in-band signal (or special character), a third step for inverting a half bit (nibble) including a redundancy bit among the bits (block) forming a pre-code when the disparity of the pre-code generated in the first step is 0 and the source data is a set in-band signal (or special character), setting the nibble-inverted pre-code as a code word and generating a complement code word which is a block-inverted code word version and a code word, a fourth step for nibble-inverting a pre-code when the disparity of the pre-code generated in the first step is not 0, setting a nibble-inverted pre-code as a code word when the disparity of the nibble-inverted pre-code is within a predefined value and generating a complement code word which is a block-inverted code word and a code word when the disparity of the set code word is not 0, a fifth step or nibble-inverting the pre-code when the disparity of the pre-code generated in the first step is not 0, manipulating the bits of the pre-code when the disparity of the nibble-inverted pre-code is not within a predefined value, manipulating the bits of the pre-code so that the disparity of the nibble-inverted pre-code is within a predefined value when the disparity of the manipulated pre-code is 0 and concurrently manipulated, setting the manipulated and nibble-inverted pre-code as a code word, and generating a complement code word which is a block-inverted code word version and a code word when the disparity of the set code word is not 0, a sixth step for selecting a code word in which the absolute value of the running digital sum (RDS) is decreased when the code with respect to the source data exists as two values of a complement code word and a code word, and a seventh step for combining the code words for a frame synchronization and generating a synchronization code word so that a unique pattern exists in a serial bit stream when the code word is converted from a parallel form to a serial form.
In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding method according to a second embodiment of the present invention which includes the steps of a first step for decoding a source data bits except for a redundancy bit from a code word when a disparity of a code word is 0 and a redundancy bit is not inverted, a second step for nibble-inverting half bits (nibble) including a redundancy bit among the bits of the code word when the dispari ty of the code word is 0 and the redundancy bit is inverted and decoding a source data bits except for the redundancy bit of the nibble-inverted code word, a third step for nibble-inverting half bits including a redundancy bit among the bits of the code word when the disparity of the code word is not 0 and has a predefined value and decoding a source data bits except for the redundancy bits from the code word when the disparity of the nibble-inverted code word is not 0 and the redundancy bit of the nibble-inverted code word is not inverted, a fourth step for nibble-inverting when the disparity of the code word is not 0 and has a pres-set value, block-inverting the bits (block) of a decode word when the disparity of the nibble-inverted code word is not 0 and the redundancy bit of the nibble-inverted code word is inverted, a fifth step for nibble-inverting when the disparity of the code word is not 0 and has a predefined value, nibble-inverting when the disparity of the nibble-inverted code word is 0 and is a synchronization or in-band signal (or special) code word, indicating an in-band signal (or special) character signal decoding the source data using the bits except for the redundancy bit from the block-inverted code word when the redundancy bit of the nibble-inverted code word is inverted, decoding the source data bits except for the redundancy bit from the nibble-inverted code word when the redundancy bit of the nibble-inverted code word is not inverted, and indicating an in-band signal (or special) character signal, a sixth step for nibble-inverting when the disparity of the code word is not 0 and has a predefined value, nibble-inverting after searching and recovering the manipulated bits when the disparity of the nibble-inverted code word is 0 and a bit-manipulated code word, decoding a source data bits except for the redundancy bit from the block-inverted code word when the redundancy bit of the recovered and nibble-inverted code word is inverted, and decoding the source data using the bits except for the redundancy bit from the recovered and nibble-inverted code word when the redundancy bit of the nibble-inverted code word is not inverted, a seventh step for decoding based on the above-described condition and process when a predefined frame synchronization pattern is detected from the code word stream and decoding a synchronization character, and an eighth step for detecting the code word as a violation when the running digital sum exceeds a predefined value or the disparity of the code word exceeds a predefined value.
In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding apparatus according to a third embodiment of the present invention which includes a disparity calculator for receiving a pre-code in which a nibble-inverted indication (NII) bit is added at the position next to the LSB of a source data of a n-bit (n represents an odd number larger than 3), computing a disparity Dpc of the pre-code, computing a disparity Dni of the odd bit nibble-inverted pre-code, decoding a code type in accordance with the value of the register and the running digital sum RDS which represent the disparity code and outputting a control signal for manipulating the bits of the pre-code; a RDS calculator for outputting a RDS which is obtained by accumulatively summing the disparity of the calculated code word by the unit of blocks for selecting a code word or a complement code word when the computed disparity Dpc is not 0; and a bit manipulator for selecting a nibble-inverted and block-inverted (NIBI) code type in accordance with a control signal from the disparity calculator, manipulating a bit of the inputted pre-code and generating a code word or a complement code word.
In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding apparatus according to a fourth embodiment of the present invention which includes a disparity calculator for receiving a block synchronized code word, calculating a disparity Dcw of the code word, computing a disparity Dni of the nibble-inverted code word, decoding a NIBI decoding type in accordance with a computed disparity value and a bit pattern of a code word and generating a control signal for manipulating the bits of the code word; a RDS calculator for outputting a RDS which is obtained by accumulatively summing the disparity Dni of the computed code word by the unit of blocks; and a bit manipulator for selecting a NIBI decoding type in accordance with a control signal of the disparity calculator, manipulating a bit of the code word, and recovering the original character.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims as a result of the experiment compared to the conventional arts.